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September 2006
HYS72T512020HR-[3.7/5]-A
240-Pin Registered-DDR2-SDRAM Modules DDR2 SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS72T512020HR-[3.7/5]-A Registered DDR2 SDRAM Modules
HYS72T512020HR-[3.7/5]-A Revision History: 2006-09, Rev. 1.11 Page All All 27,31 36 26, 27 26, 27 Subjects (major changes since last revision) Qimonda Update Adapted internet edition SPD Update Package outline figure updated Corrected IDD Currents Removed IDD6(l) from IDD specification tables
Previous Revision: 2005-05, Rev. 1.0
Previous Revision: 2005-02, Rev. 0.5
Previous Revision: 2005-02, Rev. 0.5
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03062006-TZ8J-GNDA
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1
1.1
Overview
Features
* Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type * Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_1.8 compatible * Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) * Serial Presence Detect with E2PROM * RDIMM Dimensions (nominal): 50.00 mm high, 133.35 mm wide * Qimonda Proprietary Raw Card Layout * RoHS compliant products1)
This chapter contains features and the description * 240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications * Two ranks 512M x 72 module organization with 256M x4 chip organization * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * Built with 1-Gbit DDR2 SDRAMs in P-TFBGA-68 chipsize packages.
TABLE 1
Performance for DDR2-533 and DDR2-400
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3.7 PC2-4200 4-4-4 -5 PC2-3200 3-3-3 200 200 200 15 15 40 55 Units -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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1.2
Description
driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The Qimonda HYS72T512020HR-[3.7/5]-A module family are Registered DIMM modules "RDIMMs" with 50,0 mm height based on DDR2 technology. DIMMs are available as ECC modules in 512M x 72 (4 GByte) organization and density, intended for mounting into 240-Pin connector sockets.The memory array is designed with 1-Gbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) PC2-4200 HYS72T512020HR-3.7-A PC2-3200 HYS72T512020HR-5-A 4 GB 2Rx4 PC2-3200R-333-11-ZZ 2 Ranks, ECC 1 Gbit (x4)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T512020HR-5-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200R-444-11-ZZ", where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "ZZ"
Compliance Code2) 4 GB 2Rx4 PC2-4200R-444-11-ZZ
Description 2 Ranks, ECC
SDRAM Technology 1 Gbit (x4)
TABLE 3
Address Format
DIMM Density 4 GB Module Organization 512M x 72 Memory Ranks 2 ECC/ Non-ECC ECC # of SDRAMs 36 # of row/bank/columns bits 14/3/11 Raw Card ZZ
TABLE 4
Components on Modules
Product Type1) HYS72T512020HR DRAM Components1) HYB18T1G400AF DRAM Density 1 Gbit DRAM Organization 256M x 4 Note 2)
1) Green Product 2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
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2
2.1
Pin Configuration
Pin Configuration
and Table 7 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6
TABLE 5
Pin Configuration of RDIMM
Ball No. Clock Signals 185 186 52 171 CK0 CK0 CKE0 CKE1 NC Control Signals 193 76 S0 S1 NC 192 74 73 18 Address Signals 71 190 54 BA0 BA1 BA2 NC I I I I SSTL SSTL SSTL SSTL Bank Address Bus 2 Not Connected Bank Address Bus 1:0 RAS CAS WE RESET I I NC I I I I SSTL SSTL -- SSTL SSTL SSTL CMOS Register Reset Chip Select Rank 1:0 Note: 2-Ranks module Not Connected Note: 1-Rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) I I I I NC SSTL SSTL SSTL SSTL -- Clock Enables 1:0 Note: 2-Ranks module Not Connected Note: 1-Rank module Clock Signal CK0, Complementary Clock Signal CK0 Name Pin Type Buffer Type Function
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Ball No. 188 183 63 182 61 60 180 58 179 177 70 57 176 196 174 173
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC A14 NC A15 NC
Pin Type I I I I I I I I I I I I I I I NC I NC I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL --
Function Address Bus 12:0, Address Signal 10/AutoPrecharge
Address Signal 13 Not Connected Address Signal 14 Not Connected Address Signal 14 Not Connected
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Ball No. Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38
Data Bus 63:0
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Ball No. 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bits 42 43 48 49 161 162 167 168
Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Check Bits 7:0
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Ball No. Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17
Data Strobes 17:0
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Ball No. Data Mask 125 134 146 155 202 211 223 232 164 EEPROM 120 119 239 240 101 Parity 55 Power Supplies 1 238 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197
Name
Pin Type I I I I I I I I I I I/O I I I O I AI PWR PWR
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS OD CMOS CMOS CMOS CMOS CMOS -- -- --
Function
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 SCL SDA SA0 SA1 SA2 ERR_OUT PAR_IN
Data Masks 8:0 Note: x8 based module
Serial Bus Clock Serial Bus Data Serial Address Select Bus 2:0
Parity bits
VREF VDDSPD VDDQ
I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply
VDD
PWR
--
Power Supply
2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237
GND
--
Ground Plane
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Ball No. Other Pins
Name
Pin Type NC
Buffer Type --
Function
19, 55, 68, 102, NC 137, 138, 173, 220, 221 195 77 ODT0 ODT1 NC
Not connected
I I NC
SSTL SSTL --
On-Die Termination Control 1:0 Note: 2-Ranks module Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation SSTL CMOS OD Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
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FIGURE 1
Pin Configuration for RDIMM (240 pins)
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3
3.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
This chapter lists the electrical characteristics.
This chapter contains the absolute maximum ratings table.
Parameter
Symbol
Values Min. Max. 2.3 2.3 2.3 95
Unit
Note
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ HSTG
-0.5 -1.0 -0.5 5
V V V %
1) 1) 1) 1)
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
3.2
DC Operating Conditions
TABLE 9
Operating Conditions
This chapter describes the operating conditions.
Parameter
Symbol
Values Min. Max. +55 +95 +100 +105 90
Unit
Note
DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG
PBar
0 0 -50 +69 10
C C C kPa %
5) 1)2)3)4)
HOPR
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature range all DRAM specification will be supported. Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 5) Up to 3000 m
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TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Nom. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
3) 1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
-0.30
VDDQ + 0.3 VREF - 0.125
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3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
TABLE 11
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
This chapter contains the Speed Grade Definition tables.
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- --
DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- --
Unit
Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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3.3.2
AC Timing Parameters
TABLE 12
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
This chapter contains the AC Timing Parameters.
Parameter
Symbol
DDR2-533 Min. Max. +500 -- 0.55 -- 0.55 --
DDR2-400 Min. -600 2 0.45 3 0.45 WR + tRP Max. +600 -- 0.55 -- 0.55 --
Unit Note1)2)
3)4)5)6)7)
DQ output access time from CK/CK CAS A to CAS B command period CK,CK high-level width CKE minimum high and low pulse width CK,CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
-500 2 0.45 3 0.45 WR + tRP
ps
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after tDELAY CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH --
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 375 -- -- -- +450 -- 300 + 0.25 -- -- -- -- -- --
tIS + tCK + tIH --
275 25 0.35 -500 0.35 -- - 0.25 150 25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 475 -- -- -- +500 -- 350 + 0.25 -- -- -- -- -- --
tDH(base) tDH1(base) tDIPW tDQSCK tDQSL,H
tCK
ps
tCK
ps
DQS-DQ skew (for DQS & associated tDQSQ DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK/CK Address and control input hold time
tDQSS tDS(base) tDS1(base) tDSH tDSS tFAW tHP tHZ tIH(base)
tCK
ps ps
tCK tCK
ns ns ps ps
8)
tAC.MAX
--
tAC.MAX
--
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Parameter
Symbol
DDR2-533 Min. Max. -- --
DDR2-400 Min. 0.6 350 2 tAC.MIN Max. -- --
Unit Note1)2)
3)4)5)6)7)
Address and control input pulse width tIPW (each input) Address and control input setup time DQS low-impedance from CK / CK Mode register set command to ODT update delay OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period
0.6 250 2 x tAC.MIN
tCK
ps ps ps ns
tIS(base) tLZ(DQS) tMOD
DQ low-impedance time from CK / CK tLZ(DQ)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 400 7.8 3.9 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 450 7.8 3.9 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
Mode register set command cycle time tMRD
tCK
ns ps s s ns ns
9) 10)
tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD
tHP - tQHS
-- -- -- 127.5 15 + 1tCK 0.9 0.40 7.5 7.5 0.35 x tCK 0.40 15
tHPQ - tQHS
-- -- -- 127.5 15 + 1tCK 0.9 0.40 7.5 7.5 0.35 x tCK 0.40 15
tCK tCK
ns ns
11)
Internal Read to Precharge command tRTP delay Write preamble Write postamble Write recovery time for write without Auto-Precharge
tWPRE tWPST tWR
tCK tCK
ns
Write recovery time for write with Auto- WR Precharge Internal Write to Read command delay tWTR Exit power down to any valid command (other than NOP or Deselect)
tWR/tCK
7.5 2
tWR/tCK
10 2
tCK
ns
tXARD
tCK
Exit active power-down mode to Read tXARDS command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
6 - AL 2
-- --
6 - AL 2
-- --
tCK tCK
tXP
tXSNR tXSRD
tRFC +10
200
-- --
tRFC +10
200
-- --
ns
tCK
1) For details and notes see the relevant QIMONDA component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7)
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3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) x16 (2k page size), not on 256 Mbit component 9) 0 TCASE 85 C 10) 85 C < TCASE 95 C 11) x4 & x8
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3.3.3
ODT AC Electrical Characteristics
TABLE 13
ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400
This chapter contains the ODT AC electrical characteristics tables.
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
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3.4
Currents Specifications and Conditions
TABLE 14
IDD Measurement Conditions
Parameter
Symbol
Note1)2)3)4)5)6)7)8)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD1
IDD2N
IDD2P IDD2Q
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Active Standby Current IDD3N Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
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Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max.
Symbol
Note1)2)3)4)5)6)7)8)
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 15 4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh) 7) All current measurements includes Register and PLL current consumption 8) For details and notes see the relevant QIMONDA component data sheet
TABLE 15
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
inputs are stable at a HIGH or LOW level inputs are VREF = VDDQ /2 inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
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TABLE 16
IDD Specification for HYS72T512020HR-3.7-A
Product Type Organization HYS72T512020HR-3.7-A 4G 2 Ranks x72 -3.7 Symbol Max. 1950 2130 2160 710 1650 2300 1110 720 3210 3120 3930 750 205 4740 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Unit
Note1)
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) ModuleIDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDDcurrent mode
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TABLE 17
IDD Specification for HYS72T512020HR-5-A
Product Type Organization HYS72T512020HR-5-A 4G 2 Ranks x72 -5 Symbol Max. 1770 1950 1670 610 1410 1850 870 620 2580 2490 3750 660 205 4200 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Unit
Note1)
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) ModuleIDD is calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDDcurrent mode
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3.4.1
Currents Test Conditions
TABLE 18
IDD Measurement Test Conditions for DDR2-400 and DDR2-533
For testing the IDD parameters, the following timing parameters are used:
Parameter
Symbol
-3.7 DDR2-533C
-5 DDR2-400B 3 5 15 55 40 70000 15 127.5 7.8
Unit
CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
CL(IDD) tCK(IDD) tRCD(IDD) tRC(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tRFC(IDD) tREFI
4 3.75 15 60 45 70000 15 127.5 7.8
tCK
ns ns ns ns ns ns ns s
3.4.2
On Die Termination (ODT) Current
terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The current consumption for any
TABLE 19
ODT current per terminated pin
Parameter Symbol Min. 5 2.5 10 5 Typ. 6 3 12 6 Max. 7.5 3.75 15 7.5 Unit mA/DQ mA/DQ mA/DQ mA/DQ EMRS(1) State A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0 Enabled ODT current per DQODT is HIGH; Data IODTO Bus inputs are FLOATING Active ODT current per DQODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
IODTT
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4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 20 "SPD codes for PC2-4200R-444" on Page 27 * Table 21 "SPD codes for PC2-3200R-333" on Page 31
TABLE 20
SPD codes for PC2-4200R-444
Product Type Organization HYS72T512020HR-3.7-A 4 GByte x72 2 Ranks (x4) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-4200R-444 Rev. 1.1 HEX 80 08 08 0E 0B 61 48 00 05 3D 50 02 82 04 04 00 0C 08 38 00 01
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information
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Product Type Organization
HYS72T512020HR-3.7-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Description DIMM Attributes Component Attributes
PC2-4200R-444 Rev. 1.1 HEX 07 01 3D 50 50 60 3C 1E 3C 2D 02 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 0F 51 60 37 1D 23 1E 1F
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast)
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Product Type Organization
HYS72T512020HR-3.7-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Description T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14
PC2-4200R-444 Rev. 1.1 HEX 16 43 22 2A C4 8C 61 78 11 A7 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 35 31 32 30 32 30 48 52 33 2E 37
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Product Type Organization
HYS72T512020HR-3.7-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2-4200R-444 Rev. 1.1 HEX 41 20 20 20 5x xx xx xx xx 00 FF
99 - 127 Not used
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TABLE 21
SPD codes for PC2-3200R-333
Product Type Organization HYS72T512020HR-5-A 4 GByte x72 2 Ranks (x4) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-3200R-333 Rev. 1.1 HEX 80 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 08 38 00 01 07 01 50 60 50 60 3C 1E 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
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Product Type Organization
HYS72T512020HR-5-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-3200R-333 Rev. 1.1 HEX 28 02 35 47 15 27 3C 28 1E 00 06 37 7F 80 23 2D 0F 51 60 33 1A 23 18 18 16 35 21 25 C4 8C 59 5C 11
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
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Product Type Organization
HYS72T512020HR-5-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-3200R-333 Rev. 1.1 HEX D5 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 35 31 32 30 32 30 48 52 35 41 20 20 20 20 20 5x xx xx xx xx
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Product Type Organization
HYS72T512020HR-5-A 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-3200R-333 Rev. 1.1 HEX 00 FF
99 - 127 Not used
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5
Package Outlines
FIGURE 2
Package Outline Raw Card ZZ L-DIM-240-42
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6
Product Type Nomenclature
field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 23 and for components in Table 24.
Qimonda's nomenclature uses simple coding combined with some propriatory coding. Table 22 provides examples for module and component product type number as well as the
TABLE 22
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 1G 4 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
TABLE 23
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
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Field 10
Description Speed Grade
Values -2.5F -2.5 -3 -3S -3.7 -5
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 24
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
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Table of Contents
1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 17 17 17 21 22 26 26
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Internet Data Sheet
Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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